发明名称 |
GLOBAL INPUT/OUTPUT LINE SELECTION UNIT |
摘要 |
PURPOSE: A global input/output line selection unit is provided to improve an input and an output operation of data by controlling directly enable timing of a global input/output line selection control signal. CONSTITUTION: A buffering portion(42) is used for receiving an external address signal(ext_add) and buffering the received address signal to a predetermined potential level. An address selection portion(44) is used for receiving each data bus line sense amplifier strobe from a multitude of bank and performing a latching operation by transferring selectively an address signal(gay) received from the buffering portion(42). The address selection portion(44) is controlled by a pipe input strobe signal generated from combination of the received signals. A drive portion(46) is used for generating a control signal(gio_sel) by selecting an input/output line of a bank corresponding to the address signal(gay_d) of the address selection portion(44). The address selection portion(44) is formed with an address transfer portion(47) and an address latch portion(48).
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申请公布号 |
KR20020032081(A) |
申请公布日期 |
2002.05.03 |
申请号 |
KR20000062970 |
申请日期 |
2000.10.25 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
HAN, SANG SIN;RYU, JE HUN |
分类号 |
G11C11/4096;(IPC1-7):G11C11/409 |
主分类号 |
G11C11/4096 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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