| 摘要 |
PURPOSE: A DPRAM(Dual Port RAM) interrupt controller is provided to enable a processor board to recognize an interrupt again in the case that the processor board does not recognize the interrupt generated at a processor interface board in a control station so that it makes possible a smooth DPRAM communication between the processor interface board and the processor board. CONSTITUTION: The system comprises a DPRAM(100), a processor interface board(200), a processor board(300), and an EPLD(Erasable Programmable Logic Device, 400). The DPRAM(100), installed between the processor interface board(200) and the processor board(300), stores packet data, written by the processor interface board(200), until the packet data is read by the processor board(300). The processor interface board(200) notifies the processor board of a fact that there exists packet data at a specific area of the DPRAM by receiving packet data, writing the packet data at a specific area of the DPRAM, and setting an interrupt to the processor board in a low level. The processor board(300) receives a low level interrupt signal from the processor interface board, reads the packet data stored at a specific area of the DPRAM, and transmits the packet data to a next device. The EPLD(400) receives the low level interrupt signal from the interface board(200), and transmits it to the processor board(200) while storing it for a time. But in a case that the processor board recognizes the low level interrupt signal for a time, the EPLD(400) converts the low level interrupt into the high level one for enabling the processor interface board(300) to generate an interrupt again.
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