| 摘要 |
A semiconductor integrated circuit device comprises an n-type well 8-1 formed in a p-type silicon substrate 1, an n-type well 8-2 formed so as to surround a part of the substrate 1, in which a p--type well is formed, a p--type well 15-1 formed in the substrate 1, a p--type well 15-2 formed in a part of the substrate 1, which is surrounded by the n-type well, an embedded n-type well 12-1 formed below the p-type well 15-1, and an n-type well 12-2 which is formed below the p--type well 15-2 and which is connected to the n-type well 8-2. Thus, it is possible to provide a semiconductor integrated circuit device capable of suppressing the increase of the number of photolithography steps and reducing the manufacturing costs. Alternatively, low-voltage n-channel MOS transistors QN1, QN2 and low-voltage p-channel MOS transistors QP1, QP2 are formed in a p-type well 214 and n-type well 213 of a p--type silicon substrate 211, respectively, and high-voltage n-channel MOS transistors QN3, QN4 are formed in the substrate 211. The p-type well 214, in which the transistors QN1, QN2 are formed, and the p-type element isolating layer 215 of the element isolating regions for the transistors QN3, QN4 are simultaneously formed by ion implantation using a resist mask by the lithography on a flat surface having no step. The p-type well 214 and the p-type element isolating layer 215 have the same depth from the substrate surface of the element regions and the same impurity density. Thus, it is possible to provide a semiconductor integrated circuit device capable of achieving good element isolation characteristics, and a method for producing the same.
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