| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a delay time calculated result display method for easily recognizing the conditions of the entire logical block and acquiring the detailed information of a delay time violating path. SOLUTION: A display image is constituted of a first window 101 displaying the path delay time list of the combination of the start point and end point of a path and a second window 102 displaying the cell delay time list of respective cells pertinent to the route of the path, and by selecting the path in the first window 101, the details of the path are displayed in the second window 102. Thus, the conditions of the entire logical block are recognized and the detailed information of the delay time violating path is acquired easily and the design period of a semiconductor integrated circuit is drastically shortened.</p> |
