发明名称 |
SIGNALING ARRANGEMENT |
摘要 |
<P>PROBLEM TO BE SOLVED: To deter an output signal from varying in frequency or shifting in phase by making phase comparison cycles shorter than a reference frequency. <P>SOLUTION: The signaling arrangement which makes a phase comparison between a reference signal Fref and an output signal Fout by a phase comparator to generate the output signal Fout synchronized with the reference signal Fref includes a 1st signaling means 1 which generates a signal D<SB>r</SB>varying in fixed cycles according to the reference signal Fref and outputs it to the phase comparator 3 and a 2nd signaling means 2 which generates a signal D<SB>o</SB>varying in fixed cycles according to the output signal Fout and outputs it to the phase comparator 3. <P>COPYRIGHT: (C)2004,JPO |
申请公布号 |
JP2003324347(A) |
申请公布日期 |
2003.11.14 |
申请号 |
JP20020128845 |
申请日期 |
2002.04.30 |
申请人 |
ANDO ELECTRIC CO LTD;KYUSHU ANDO DENKI KK |
发明人 |
SUGIMORI MASAYASU;TOYODA SEIJI;OTSUKA YOSHIAKI |
分类号 |
H03L7/08;H03L7/18;H03L7/181 |
主分类号 |
H03L7/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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