| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve a problem occurring when a high speed interconnect circuit is tested by a test method of DC and AC coupled interconnect circuit based on conventional IEEE1149.1TAP and JTAG and to provide a method and an apparatus for enabling to perform high speed test of an interconnect circuit including a JTAG boundary scan cell while minimizing the additional circuit. <P>SOLUTION: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction are added to the interconnect circuit test method of a circuit including a conventional JTAG boundary scan cell. These additional instructions extends conventional JTAG operation and enables the test of the high speed interconnect circuit. <P>COPYRIGHT: (C)2004,JPO |
