Optimized read data amplifier and method for operating the same in conjunction with integrated circuit devices incorporating memory arrays

摘要

An optimized read data amplifier for the output data path of integrated circuit memory arrays comprises a fast, low power and small on-chip area consuming circuit which is advantageously effectuated through the combined application of "current sensing" and "voltage sensing" techniques. In a particular embodiment disclosed herein, an amplifier enable signal is timed with the column read address so that the amplifier is turned "off" when not in use and both data read lines ("DR" and "DRB") are precharged "high". No clocking of the read data amplifier is required in order to obviate undesired clock latencies and pipelining and a simple mechanism is implemented such that control of power-up and power-down results in further power savings.