| 摘要 |
Techniques for dynamically shifting the phase of clock signals are provided. A circuit generates a plurality of periodic clock signals. Each clock signal has the same period, the same duty cycle, and a different phase. The clock signals are provided to the inputs of two multiplexers. The output signals of the multiplexers are transmitted to a phase selection circuit that generations phase selection signals. The multiplexers each select one of the clock signals in response to the phase selection signals. When the phase selection signals change value, each multiplexer selects a different clock signal in order to shift the phase of its output signal forward or backward by an incremental value. A directional signal determines whether the multiplexers shift the phases of their output signals forward or backward in time.
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