发明名称
摘要 <p>A packet switch has a switch section formed by a plurality of crossbar switch planes and plurality of interfaces, and each interface outputs in parallel input packets in block units to the plurality of crossbar switch planes in response to signals from a scheduler, wherein when n crossbar switch planes can be mounted on the packet switch, each interface allocates time slots corresponding to the n crossbar switch planes or when a switch plane is additionally mounted, a block is read at a time slot corresponding to the additional switch plane or when a switch plane is stopped from working, an idle time slot is used to prevent a block from being output to the switch plane which is unused.</p>
申请公布号 JP3736338(B2) 申请公布日期 2006.01.18
申请号 JP20000350555 申请日期 2000.11.13
申请人 发明人
分类号 H04Q3/52;H04L12/931;H04L12/937;H04L12/939 主分类号 H04Q3/52
代理机构 代理人
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