| 摘要 |
A one device per bit random access memory cell and array is constructed with integrated circuit MOSFET transistors as the memory cell switching elements. Information transfer is accomplished by transferring incremental charges between a capacitor to a sense bit line. The capacitor is comprised of a region disposed in the substrate and a constantly charged polycrystalline plate insulatively disposed above the semiconductor substrate. The MOSFETS have a merged sense line and source region and have omitted a separate diffusion for their drain region by merging the drain with the capacitor region. The storage devices are grouped in pairs and share a common gate member and a common capacitive plate. Therefore, a single contact window is provided to the common gate member and the use of one half of the minimum contact area is allocated per device. By means of an interdigitated topology, a memory cell pair is devised having a small field area with a relatively large cell to bit line capacitance ratio.
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