发明名称 |
BALANCING PROGRAMMING SPEEDS OF MEMORY CELLS IN A 3D STACKED MEMORY |
摘要 |
Programming techniques for a three-dimensional stacked memory device provide compensation for different intrinsic programming speeds of different groups of memory cells based on the groups' locations relative to the edge of a word line layer. A larger distance from the edge is associated with a faster programming speed. In one approach, the programming speeds are equalized by elevating a bit line voltage for the faster programming memory cells. Offset verify voltages which trigger a slow programming mode by elevating the bit line voltage can also be set based on the group locations. A programming speed can be measured during programming for a row or other group of cells to set the bit line voltage and/or the offset verify voltages. The compensation for the faster programming memory cells can also be based on their speed relative to the slower programming memory cells. |
申请公布号 |
WO2016209563(A1) |
申请公布日期 |
2016.12.29 |
申请号 |
WO2016US34997 |
申请日期 |
2016.05.31 |
申请人 |
SANDISK TECHNOLOGIES LLC |
发明人 |
MUI, Man L.;SUN, Yongke;DONG, Yingda |
分类号 |
G11C16/34 |
主分类号 |
G11C16/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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