发明名称 |
Channel control circuit and semiconductor device having the same |
摘要 |
A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal. |
申请公布号 |
US9207281(B2) |
申请公布日期 |
2015.12.08 |
申请号 |
US201313845254 |
申请日期 |
2013.03.18 |
申请人 |
SK Hynix Inc. |
发明人 |
Kim Ki Tae |
分类号 |
G01R31/28;G01R31/3185 |
主分类号 |
G01R31/28 |
代理机构 |
William Park & Associates Ltd. |
代理人 |
William Park & Associates Ltd. |
主权项 |
1. A channel control circuit having a plurality of channels, comprising:
a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal in response to the clock buffer control signal, wherein the clock output signal is used as an internal clock of a semiconductor device. |
地址 |
Gyeonggi-do KR |