发明名称 SYNCHRONOUS INFORMATION PROCESSOR
摘要 <p>PURPOSE:To make it possible to facilitate a check on the phase margin of TM signals and phase adjustment, by providing a TM control circuit that varies individually the phase and pulse width of a random TM signal of a polyphase timing TM signal. CONSTITUTION:A plurality of TM signals Tn bearing a prescribed phase relation are generated by TM generating circuit part 1 and sent to TM control circuit part 2. In circuit part 2, signals Tn are inputted to one-side terminals of AND gates 10 and 11 and to the other-side terminals of gates 10 and 11, delay control signals CTL1 and CTL2 are inputted respectively. When signal CTL1 is at ''1'', signal Tn is outputted as TM signal T'n delayed by two gates, gate 10 and OR gate 13. When signal CTL2 is at ''1'', signal Tn is outputted as signal T'n delayed by three gates, gate 10 and OR gate 12 and 13. When signals CTL1 and CTL2 are both at ''1'', the pulse width of signal T'n becomes greater than that of signal Tn nearly by the delay time of gate 12.</p>
申请公布号 JPS5688518(A) 申请公布日期 1981.07.18
申请号 JP19790165553 申请日期 1979.12.21
申请人 HITACHI LTD 发明人 AMARI MITSUHIRO;OKABE TOSHIHIRO
分类号 G06F1/06;G06F1/04 主分类号 G06F1/06
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