| 摘要 |
PURPOSE:To prevent the prolongation of operation time due to an overflow, by providing a selector which supplies either a maximum or a minimum, expressed by the number output bits of an adder, to a latch register as the sum in case of the overflow. CONSTITUTION:An adder 11 calculates the sum of data inputted to terminals A dnd B, and supplies the most significant digit bit to a digit overflow detecting circuit 13 through a line 16 while supplying the sum to a selector 14 through a line 15. This circuit 13 is further supplied with the most significant digit bit of input data through a line 17 and also supplied with the most significant digit bit of a latch register 12 which holds the sum output through a line 18. The output of the circuit 13 is supplied as a selection signal to the selector 14, which is further supplied with the normal addition result output of the adder 11 through a line 15. Constant data, i.e. a maximum value X'7FFF' and minimum value X'8000', expressed by the output bit width of the adder 11 are supplied through lines 19 and 20 respectively. |
