Clock controlled dual slope voltage to frequency converter.

摘要

Clock-controlled dual slope voltage to frequency converter has an integrator supplying a charging ramp to a threshold detector. The slope of the ramp depends on the input voltage to the integrator and the threshold detector is triggered by the ramp to enable a pulse from a clock to generate a constant current discharge pulse. The discharge pulse is fed to the integrator to produce a discharge ramp back below the threshold. The frequency output is taken from the output of the threshold detector to be synchronous with triggering of the detector.