Adjustment of write timing in a memory device

摘要

A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

主权项

1. A method for adjusting a write timing in a memory device, comprising:
sending a data signal, a write clock signal, and a reference signal to the memory device; receiving a sampled reference signal from the memory device; computing phase measurements of the sampled reference signal over a period of time; comparing the computed phase measurements of the sampled reference signal over the period of time; computing a phase error signal based on the compared phase measurements; and adjusting a phase difference between the data signal and the write clock signal based on the phase error signal, the adjusting comprising:
sampling the sampled reference signal;detecting a phase of the sampled reference signal; andcomparing the phase of the sampled reference signal over the period of time to adjust the phase difference.