| 摘要 |
An integratable decoding circuit to decode information which is represented by input signals (A1, A2, An; /A1, /A2, /An) is presented. It is made in CMOS technology, with n transistors of one channel type (M1, M2, Mn), and n transistors of the other channel type (T1, T2, Tn). In operation, its decoder output (DA) at every moment within a clock period (TP) is at a defined signal level (L, H). There is thus no pre-charging and then de-energising of a pre-charging transistor, which would result in floating of the output in the unselected state. The decoding circuit is particularly suitable for use in integrated semiconductor memories. <IMAGE>
|
