PROGRAMMABLE INPUT/OUTPUT DELAY BETWEEN ACCESSES

摘要

A design which allows for the addition of a programmable delay between back-to-back I/O cycles in a computer system is shown. The addition of the programmable delay allows utilization of the minimum amount of delay between back-to-back I/O cycles that is required to maintain compatibility between the computer system and the particular 8-bit or 16-bit I/O devices being used. A programmed value reflecting a particular length of delay is used to generate a signal that is pulse position modulated with this length of delay. The pulse position modulated signal is used in conjunction with a counter that counts out a predetermined length of delay dependent on the particular I/O cycle that has just been completed. The pulse position modulated signal terminates the delay being provided by the counter when the programmed length of delay has expired.