| 摘要 |
PURPOSE:To reduce the tendency of a decreased processing capability more than that of single link control when multi-link control of a packet is implemented. CONSTITUTION:The system is provided with a register 6 having a contention control circuit 5 so as to access a multi-link frame reception order number and a multi-link frame is connected to each single link control signal 4. In order that the single link control section 4 gives a received multi-link frame sequentially to a packet control section 7 through a multi-link frame generating section 1, the system is provided with a comparison means comparing whether or not the multi-link sequence number in the register 6 and the number of the multi-link frame received by each single link control section 4 are coincident, a transfer enable means updating a multi-link sequence number in the register 6 when the result of comparison indicates coincidence and enabling the transfer of the relevant multi-link frame, and a latch means latching the multi-link frame to the single link control section 4 when the result of comparison indicates dissidence.
|
