Interleaved RISC-type parallel processor and processing methods.

摘要

A pipelined, RISC-type processor operated in parallel mode and its associated processing methods are described for separately handling instructions from multiple program instruction sets. In a specific embodiment, the pipelined processor includes an instruction fetch unit, an instruction decode unit and n execution units. Each execution unit operates at substantially the same process cycle time, while the speed of operation of the instruction fetch unit and instruction decode unit is at least n times this cycle time of the execution units such that each phase of the pipeline separately processes n instructions substantially within one machine cycle. Timing and control circuitry is coupled to each of the principle elemental units for controlling the timing and sequence of operations on instructions. In comparison with prior art RISC-type architectures, the hybrid parallel processor increases instruction throughput without changing technology or requiring a more complex instruction set. This is accomplished by maximizing utilization of the faster elemental phases in the processing pipeline. Corresponding processing methods for such a parallel pipelined processor are also discussed. <IMAGE>