| 摘要 |
<p>A read/write memory, such as a static random access memory, is disclosed in which equilibration of differential data lines, such as bit lines or input/output lines, is performed at the beginning of each cycle. The memory includes a write circuit, for example associated with each sense amplifier, for driving the differential data lines with a data state corresponding to input data during a write operation. The write circuit is controlled by a write enable signal which, in this memory, is interlocked with the equilibration signal. As a result, the write operation is disabled during equilibration of the differential data lines. Since equilibration is maintained during address transitions, the write operation is only enabled during stable address periods, thus eliminating the possibility of a write to the address of a prior or subsequent cycle. <IMAGE></p> |
