发明名称 |
TRENCH LITHOGRAPHY PROCESS |
摘要 |
A process of forming an integrated circuit using a dual damascene interconnect process by etching a via hole in an ILD and filling the via hole with a sacrificial via fill material. A trench etch hard mask layer is formed over the ILD. An inorganic hard mask layer is formed over the trench etch hard mask layer. The inorganic hard mask layer is etched to form an etch mask for the trench etch hard mask layer, which is subsequently etched to form an etch mask for the trench etch process. The sacrificial via fill material etches at a comparable rate to the ILD layer. The trench etch hard mask layer is removed and the sacrificial via fill material is removed from the via hole.
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申请公布号 |
US2012100717(A1) |
申请公布日期 |
2012.04.26 |
申请号 |
US201113280601 |
申请日期 |
2011.10.25 |
申请人 |
LII TOM;KIRMISE KAREN HILDEGARD RALSTON;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
LII TOM;KIRMISE KAREN HILDEGARD RALSTON |
分类号 |
H01L21/768;H01L21/302 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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