| 发明名称 |
Computer having a parallel operating capability. |
| 摘要 |
<p>A RISC processor is arranged to reduce a code size, make the hardware less complicated, execute a plurality of operations for one machine cycle, and enhance the performance. The processor is capable of executing N instruction each having a short word length for indicating a single operation or an instruction having a long word length for indicating M (N<M) operations. When the number of operations to be executed in parallel is large, the long-word instruction is used. When it is small, the short-word instruction is used. A competition between the long-word instructions is detected by hardware and a competition between the short-word instructions only is detected by software. The simplification of the hardware brings about improvement of a machine cycle, improvement of a code cache hit ratio caused by the reduction of a code size and increase of the number of operations to be executed in parallel for the purpose of enhancing the performance. <IMAGE></p> |
| 申请公布号 |
EP0551090(A2) |
申请公布日期 |
1993.07.14 |
| 申请号 |
EP19930100067 |
申请日期 |
1993.01.05 |
| 申请人 |
HITACHI, LTD. |
发明人 |
HOTTA, TAKASHI;NAKATSUKA, YASUHIRO;TANAKA, SHIGEYA;YAMADA, HIROMICHI;MAEJIMA, HIDEO |
| 分类号 |
G06F9/30;G06F9/318;G06F9/38 |
主分类号 |
G06F9/30 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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