发明名称 FLATTENING OF WIRING LAYERS
摘要 PURPOSE:To realize a method of manufacturing a multilayer wiring substrate having no surface flaw and no exposure failure of wiring conductor layer by forming the surface of wiring conductor layer and insulating layer of the uniform thickness with the etch back method. CONSTITUTION:Resist patterns 31a to 31d are formed on a base conductor 12 for the plating provided on a base substrate. A preliminary conductor layers 32a to 32c for wiring is formed thicker than the film thickness of resist patterns 31a to 31d by burying an aperture provided in the outside of the resist pattern and the preliminary conductor layer for wiring projected from the aperture is polished up to the resist pattern surface to form the flat conductor layers 35a to 35c for the wiring. Next, after the conductor for wiring is covered with the preliminary film for insulating layer, a film sacrified by flattening is laminated and the preliminary films for insulating layers 40a to 40d is etched back by the etch back method for the flattening until the conductive layers 37a to 37c for wiring are exposed.
申请公布号 JPH0653660(A) 申请公布日期 1994.02.25
申请号 JP19920202435 申请日期 1992.07.29
申请人 OKI ELECTRIC IND CO LTD 发明人 TAKAHASHI YOSHIRO;KASUYA YUKIO;KARASUNO YUTAKA
分类号 H05K3/22;H05K3/46;(IPC1-7):H05K3/46 主分类号 H05K3/22
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