发明名称 ADDRESS-MATCHING STRUCTURE WITH REFERENCE TO REDUNDANT STRUCTURE OF DRAM
摘要 PURPOSE: To minimize the number of necessary blown fuses by controlling the cut of a control fuse in accordance with the number of addresses on logic '1' or '0' and cutting the fuse corresponding to the address. CONSTITUTION: The fuse C of an auxiliary circuit 27 having invertors 28, 30 and 32, 34 which are mutually connected is not blown when the number of the logic '0' states of address bits A0 -A11 is smaller than that of the logic '1' states. The fuses 0-11 corresponding to the addresses A0 -A11 of the low levels with logic '0' are cut. When the number of the address bits of logic '0' is large, and the fuse C is blown the fuses 0-11 whose addresses are logic '1' are blown. Thus, the number of fuses which are necessary is minimized compared with the case when the fuses are cut in accordance with the zero of the address by cutting the corresponding fuses in accordance with logic '1' or '0' on the address.
申请公布号 JPH06195995(A) 申请公布日期 1994.07.15
申请号 JP19920111757 申请日期 1992.04.30
申请人 TEXAS INSTR INC <TI> 发明人 SUKEGAWA SHUNICHI;HIIPU BAN TORAN
分类号 G11C11/408;G11C29/00;G11C29/04;(IPC1-7):G11C29/00 主分类号 G11C11/408
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