| 摘要 |
This system provides a circuit and method which checks the erased state and maintain the optimal erased state of memory cell at selected page. The circuit comprises: an EEPROM which consists of a memory cell array (100), a low and a column decoders (900, 400) , an address buffer (800), a data input/ output buffer (600), and a program latch circuit (1000); an erasion detecting means (200) for outputting detecting signals (4,5) by using output state of the column decoder; a sequential output means (240) for outputting control signals (6,7,8) of high voltage level; and an address counter (500) for providing address counting clocks (9,10,11).
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