| 摘要 |
A data processor that includes an interrupt controller, a condition code register, a condition code stacking register, a data memory with a stacking area, a data processing unit, and an interrupt request decoder. The interrupt controller receives interrupt request signals including a break interrupt request signal and a plurality of standard interrupt request signals. The condition code register stores condition code values including a data processor mode control value. The data processing unit performs data processing operations. The data processing operations are suspended when the data processor mode control value is set to a predefined "sleep mode" value and are enabled when the data processor mode control value is set to a predefined "run mode". The interrupt decoder responds to a received break interrupt request signal by generating: (A) first, condition code register control signals to copy the mode control value stored in the condition code register into the condition code stacking register, (B) second, condition code register control signals to set the mode control value to-the predefined "run mode" value. It responds to a standard interrupt request signal by generating: (A) first, condition code register control signals to set the mode control value to the predefined "run mode" value; and (B), second, condition code register control signals to copy the mode control value stored in the condition code register into the data stacking area.
|
