| 摘要 |
A microprocessor employing a DSP unit and an instruction decode unit is provided. The instruction decode unit is configured to detect an instruction field included with an instruction, and to dispatch instructions having the instruction field to the DSP unit. The DSP unit performs DSP functions, such as a multiply-accumulate function. In one embodiment, the inclusion of an instruction prefix field in an x86 instruction indicates that the instruction is a DSP instruction. In one particular implementation, the inclusion of a segment override prefix byte within the prefix field of an x86 instruction indicates that the instruction is a DSP instruction. Embodiments of the DSP unit may include a vector memory for storing operands. A block of operands may be stored into the vector memory prior to initiating a large number of DSP operations upon the block of operands.
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