The DRAM includes a memory cell array with cells in a matrix formation and provided with numerous bit lines (BL), for signal transmission to the cells, being crossed by word lines (WL) for cell selection. Corresponding measuring amplifiers (SA) are provided for data read-out on the bit lines. Also provided are column selection circuits and several control signal lines (LCSL,MCSL) coupled to the selection circuits. The amplifier data are transmitted to the cell array outer side by data lines (LDQ, MDQ) containing two wiring layers. The column selection circuits control the data line connections to the amplifiers. Each control signal line contains a further two wiring layers.
