| 摘要 |
<p>A frequency-dividing circuit comprises a digital accumulator capable of performing signed arithmetic and means for adding of a predetermined numerator to the content of the accumulator. Means are provided for subtracting a predetermined denominator from the content of the accumulator and further means detect if the value held in the accumulator has become zero or negative and establishing a delay setting value dependent upon the held value. Further means convert the delay setting value into a time delay inversely proportional to the magnitude of the delay setting value and the yet further means change the state of a digital output signal on expiry of the said time delay. A corresponding method is also disclosed.</p> |
