| 摘要 |
The circuit includes a control device intended to create data used for control purposes and to insert this data between the existing packets. This is in the form of a control packet which is transmitted in the packet stream to the series interface bus (BS). The circuit incorporates two (104a, 104b) memories, and a control device intended to regulate the control data, giving an instruction to write control data into the first memory and to transmit control data when it is necessary to do so. First and second transmission circuits (106, 107) are also incorporated. The second transmission circuit puts back to zero the control data established by the control device when the transmission of the control pack is ended. |
