| 摘要 |
<p>PROBLEM TO BE SOLVED: To make it unnecessary to consider dispersion in the manufacturing process and the variation of power source voltage in timing design, to reduce the period of timing design and to curtail manufacturing cost by digitalizing timing adjustment with an integer times of the delay stages of the first to n-th clock generating circuits. SOLUTION: A multi-phase clock generating circuit 26 delays a clock CLKi through 2 m, 4 m, 6 m-2 nm inverters and generates clocksϕ1 toϕn whose phases are formed by shifting the phase of the clock CLKi byθto nθwhere m is a natural number. A timing adjusting circuit 22 determines the timings of the activated point and inactivated point of the control signal CNT by counting the clocksϕ1 toϕn generated by the generating circuit 26 to supply the timing control signal CNT to a DRAM core 3 through a timing buffer circuit 27. Thus timing adjustment is digitalized with an integral multiple of the delay stage in the generating circuit 26.</p> |
