| 摘要 |
A shared memory parallel processing system interconnected by a multi-stage netwo rk combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the net work. The system configuration techniques include a systematic method for partitioning and contro lling the memory in relation to local versus remote accesses and changeable versus unchangeable d ata. Most of the special-purpose hardware is implemented in the memory controller and network ada pter, which implements three send FIFOs and three receive FIFOs at each node to segregate an d handle efficiently invalidate functions, remote stores, and remote accesses requiring c ache coherency. The segregation of these three functions into different send and receive FIFOs great ly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.
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