| 摘要 |
The present invention relates to an arrangement and a method of controlling time during or after layout of a digital logical circuit system comprising a number of building blocks (2b,4b,6b) each comprising a number of cells and a number of clocked first register cells (1b',3b',5b',7b'), e.g. one for each building block and responsible for activation of the cells of the building blocks. A cell library is provided containing information about available cells and at least one system clock and/or subsystem clock with a given target frequency clocking the register cells is provided. A number of alternative register cells are provided in the cell library which have a number of different setup and hold characteristics with respect to the clock arrival and means are provided for substituting first register cells through appropriate alternative register cells without changing the construction and layout of the circuit system. |
