发明名称 HIGH SPEED CLOCK ENABLE LATCH CIRCUIT
摘要 PROBLEM TO BE SOLVED: To drastically reduce the setup/holding time by generating an output signal having a first or second signal scale based on the scale of an input signal at the terminal of an initialization mode at an output mode. SOLUTION: Input switches 140 and 145 are opened as a result that a clock signal CLK is changed to a first signal level. The voltage scales of the parts IN and the inverse of IN of respective input signals at transistors 112 and 132 are kept in scales when the switches are opened irrespective of the subsequent change of the input signal parts during the period of the output mode. Namely, second and fourth transistors 110 and 130 are kept in a biased state to the same level as that given by the input signal parts IN and the inverse of IN at a moment when the clock signal CLK is shifted to a first signal period from a second signal period. An initialization switch 150 is opened with the shift and first and second junction parts 115 and 135 are mutually cut and they operate with the different voltage scale.
申请公布号 JPH11168359(A) 申请公布日期 1999.06.22
申请号 JP19980222627 申请日期 1998.08.06
申请人 LUCENT TECHNOL INC 发明人 GABARA THADDEUS JOHN
分类号 H03K3/356;H03M9/00;(IPC1-7):H03K3/356 主分类号 H03K3/356
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