| 摘要 |
<p>Multi-processor system (10) includes at least two processors, a system bus (30) providing communication between the processors, and an arbiter (60) generating system responses on the bus. In response to an invalidation request of a cache line, one of the processors generates a system response, casts back and updates the state of that cache line to a transition cache (110) which, depending upon the response, either discards the cast back or converts the cast back into a command for writing the cache line in main memory (40). The processor also converts an exclusive read command requiring a reservation to a non-exclusive read command if that reservation has been lost prior to placing the command on the bus (30). The transition cache (110) may shift the memory coherency image state for a non-exclusive command, which is waiting for data to return, if a command associated with the requested address is snooped.</p> |
