| 摘要 |
<p>An IC tester of a multiple way interleaving type capable of testing an IC whose latency (N) (the number of delayed cycles) is either even or odd. A plurality of sets of test circuit units (4-1 and 4-2) each comprise a clock control circuit (23), which includes an adder (21) for summing the test period Tr of the IC tester and a set clock period Tc and a selector (22) for selecting either the output from the adder or the set clock period Tc. A latency is set in a delay setting register (5) that supplies the selector with '0 and 1' if the latency is even and odd, respectively.</p> |
