| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a signal matched and synchronized with a clock signal in time, while having one pulse corresponding to each pulse of an input signal. SOLUTION: This signal synchronizing circuit is constituted with counters 1 and 11 for receiving an input signal 6 and dividing its frequency into two stages (÷2) and a D type flip-flop 2 for latching an output 14 of the frequency- having counter at the time determined by a clock signal 10, an output 15 of this flip-flop is stabilized by sampling it through another flip-flop 3 again, a signal 16 is coupled with a delay signal 17 of that signal prepared by further another flip-flop 4, while using an exclusive OR gate 12.</p> |
