Frequency division

摘要

A frequency divider comprises a signal generation stage arranged to employ a clock at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal. A synchronization stage is arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal.

主权项

1. A frequency divider comprising:
a signal generation stage arranged to employ a clock signal at a clock frequency to provide a first reference signal and a second reference signal, the second reference signal corresponding to the first reference signal delayed by half a period of the clock signal; a synchronization stage arranged to generate an output signal having an output frequency divided from the clock frequency by switching between the first reference signal and the second reference signal once per cycle of the output signal; and a mode control stage coupled to the signal generation stage for generating a selection signal indicative of the completion of each cycle of the first reference signal, and wherein the switching between the first reference signal and the second reference signal is responsive to the selection signal.