发明名称 CLOCK RELOADING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To easily avoid a slip without changing the readout order of readout addresses by writing input data to a storage means according to write addresses, reading the input data out according to the readout addresses, alternately placing read and write means in operation, and selecting and outputting input data read out by a read and write means in operation. SOLUTION: Memories 10-1 and 10-2 of systems 1 and 2 are placed in operation by turns, in with of frames, by using input frame pulses and the memory 10-1 of the system 1 are placed in writing and reading operation by a choice 1 and a choice 2 for the 1st frame of input data. By using different memories for each frame, both the write and read addresses overlap with each other, even at the place where the reading of a last frame as a slip occurrence place and the writing of a next frame overlap with each other, so that a slip can be avoided without varying a WR-RD address initial phase difference and the memory capacity and changing the readout order of RD addresses.</p>
申请公布号 JP2000269941(A) 申请公布日期 2000.09.29
申请号 JP19990069306 申请日期 1999.03.15
申请人 NEC MIYAGI LTD 发明人 ENDO HIROYUKI
分类号 H04L7/00;(IPC1-7):H04L7/00 主分类号 H04L7/00
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