| 摘要 |
An ESD protection device for use with an integrated circuit that provides a low impedance resistive path between IC pads (including Vdd and Vss pads) when power to the IC is off, while assuring adequate isolation between the IC pads when the power is on. The device includes a semiconductor substrate (typically a p-type Si substrate) and at least two vertically integrated pinch resistors formed in the semiconductor substrate. Each of the vertically integrated pinch resistors is connected to a common electrical discharge line and to a pad. Each of the vertically integrated pinch resistors includes a deep well region and a first surface well region, both of the second conductivity type (typically n-type). The first surface well region circumscribes the deep well region, thereby forming a narrow channel region of the first conductivity type (e.g. p-type) therebetween. When no potential is applied to the first surface well regions (i.e. power is off), the two vertically integrated pinch resistors connected by the common electrical discharge line provide a low impedance resistive path between the pads for shunting ESD current. When a potential is applied to the first surface well region by the IC power supply (i.e. power is on), however, the width of the narrow channel region is pinched-off due to a potential-produced depletion region in the narrow channel region, thereby isolating the pads from each other. A process for the formation of the ESD protection device involves sequential formation of each of the device regions in a semiconductor substrate.
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