| 摘要 |
The invention concerns a frequency synthesis method, whereby the output signal frequency of a frequency synthesizing device is compared in a fractional division phase locked loop to that of a reference signal delivered, directly or after frequency division, by a generator whereof the frequency can be modified in controlled manner, the division code or factor of the phase locked loop being supplied by a Sigma-Delta converter. Said method is characterised in that it consists in modifying the frequency (Fref) of the reference signal (Sref) to compensate a possible shift in the frequency (Fout) of the output signal (Sout) relative to the desired frequency (Ftheo).
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