METHOD FOR FABRICATING HIGH-SPEED TRANSISTOR

摘要

PURPOSE: A method for fabricating a high-speed transistor is provided to restrain a gate depletion phenomenon in a gate electrode of high density by implanting dopants of high density to a gate electrode of an NMOS transistor, selectively. CONSTITUTION: An N well region(11) and a P well region(13) are formed on a P type silicon substrate(10). An isolation oxide layer(15) is formed on a part of the N well region(11) and a part of the P well region(13). A gate oxide layer(17) is grown on the N well region(11) and the P well region(13). A polysilicon layer is deposited on the silicon substrate(10). A pattern of the first gate electrode(33) is formed on a part of the gate oxide layer(17) of the P well region(13). A pattern of the second gate electrode(35) is formed on a part of the gate oxide layer(17) of the N well region(11). The first and the second electrodes(33,35) are formed thereon. A nitride layer is deposited on the silicon substrate(10). A spacer(37) is formed at sidewalls of the first and the second gate electrodes(33,35). A salicide layer(39) is deposited on the first and the second gate electrodes(33,35) and a source/drain region of the first and the second MOS transistors. A planarization layer(41) is deposited on the silicon substrate(10). The planarization layer(41) of the P well region(13) is exposed. A pattern of a photo-resist layer(43) is formed on the remaining planarization layer(41). N type dopants are implanted into the first gate electrode(33). The pattern of the photo-resist layer(43) is removed. An insulating layer is deposited on the planarization layer(41).