发明名称 |
Arrangemenet in a power MOS transistor |
摘要 |
To reduce parasitic capacitances between drain and source electrodes, respectively, and gate electrodes in a power MOS transistor, the drain and the source electrodes (D', S') are located below the gate electrodes (G) in the transistor.
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申请公布号 |
US2002027242(A1) |
申请公布日期 |
2002.03.07 |
申请号 |
US20010918726 |
申请日期 |
2001.08.01 |
申请人 |
ZACKRISSON MIKAEL;AF EKENSTAM NILS;JOHANSSON JAN |
发明人 |
ZACKRISSON MIKAEL;AF EKENSTAM NILS;JOHANSSON JAN |
分类号 |
H01L29/417;H01L29/78;(IPC1-7):H01L29/76 |
主分类号 |
H01L29/417 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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