发明名称 POWER CONSUMPTION REDUCING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To reduce power consumption by turning into a waiting state, and to reduce power consumption even in a normal operation. SOLUTION: This circuit is provided with an oscillation amplitude level detecting circuit 3 for monitoring the amplitude level of an oscillation signal e being a clock signal supplied from an oscillation circuit 4 which operates with an operating voltage d, and for outputting a boosting signal c when the deterioration of an amplitude level E due to the decrease of the operating voltage d is made not more than a preliminarily set lower limit level G and a voltage variation regulator 4 for controlling the operating voltage d according to the supply of the boosting signal c. Thus, the operating voltage d is reduced to almost a limit with which a stable operation can be ensured by a system logic 5 in a normal operation so that the power consumption can be reduced even in the normal operation.</p>
申请公布号 JP2002091605(A) 申请公布日期 2002.03.29
申请号 JP20000276818 申请日期 2000.09.12
申请人 NEC MICROSYSTEMS LTD 发明人 KAMIKIZAKI SUMIYUKI
分类号 G06F1/32;G06F1/04;(IPC1-7):G06F1/04 主分类号 G06F1/32
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