Successive approximated register analog-to-digital converter and conversion method thereof

摘要

A Successive Approximated Register Analog-to-Digital Converter (“SARADC”) is provided that includes: a bootstrapping unit that receives and samples analog signals; and an Analog-to-Digital Conversion Unit (“ADCU”) that converts the analog signals into digital signals and outputs the digital signals. ADCU has a resolution increasing in response to an intentionally injected offset voltage. In this case, ADCU includes Capacitor Arrays (“CAs”) having: a differential structure each including reference voltage application capacitors having different capacitances and an Offset Voltage Injection Capacitor (“OVIC”); a delay cell that operates CAs in an asynchronous mode; Reference Transfer Switch Units (“RTSUs”) that apply a reference voltage to CAs; a comparator that compares output voltages of CAs; and Successive Approximated Register Logics (“SARLs”). SARLs control operations of RTSUs in response to an output signal of the comparator and perform control so that a reference voltage is applied to OVICs when the output of the comparator is abnormal.

主权项

1. A successive approximated register analog-to-digital converter, comprising:
a bootstrapping unit that receives and samples first and second analog signals; and an analog-to-digital conversion unit that converts the first and second analog signals into digital signals, and outputs the digital signals, the analog-to-digital conversion unit having a resolution increasing in response to an intentionally injected offset voltage; wherein the offset voltage is a voltage value at which a bit error rate (BER) according to a value of the offset voltage is close to 0.