High-gain locked-loop phase detector

摘要

Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

主权项

1. A method of operation within in a locked-loop circuit, the method comprising:
generating pairs of phase-error pulses during respective cycles of a reference clock signal, each pair of phase-error pulses including an up pulse and a down pulse having respective durations that (i) sum to a substantially constant duration briefer than half the period of the reference clock signal and (ii) have a difference indicative of a time-varying phase difference between the reference clock signal and a feedback clock signal; and iteratively adjusting the phase of the feedback clock signal according to the difference between the up pulse and down pulse durations of respective pairs of the phase-error pulses.