Enhanced computer processor and memory management architecture

摘要

Disclosed in some examples is an improved computing architecture, which includes multiple processor cores and I/O devices communicating with multiple memory banks using a High Speed Interconnect Unit (HSU). The HSU quickly routes (e.g., in one clock cycle) a memory access request from an I/O device or a processor core to a particular memory bank over one of a number of independent memory routes, each memory route servicing a particular memory bank. The routing is based upon the values of preselected bit positions (“preselected bits”) in the requested memory address, the preselected bits being chosen so as to maximize the distribution of memory accesses of the entire system across all available memory banks (and by extension distributing the memory accesses across the available memory routes).

主权项

1. A computing system comprising:
An interconnect unit comprising:
a plurality of processor cores;a plurality of address resolution units (ARU), each ARU servicing memory requests for only one of the plurality of processor cores and communicatively coupled to the processor core it services;a plurality of memory routes, each memory route communicatively coupled to each of the plurality of ARUs and to each of a plurality of memory interfaces;each of the ARUs configured to:
receive a memory request from the processor core it services;select one of the plurality of memory routes based upon a predetermined subset of a plurality of address bits in the memory request; andtransmit the memory request over the selected memory route to each of the plurality of memory interfaces.