发明名称 |
Method and apparatus providing non level one information caching using prefetch to increase a hit ratio |
摘要 |
A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1 instruction caching that uses prefetch to increase the hit ratio. Cache lines in a cache set are buffered, wherein the cache lines have a parameter indicating data selection characteristics associated with each buffered cache line. Then which buffered cache lines to cast out and/or invalidate is determined based upon the parameter indicating data selection characteristics.
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申请公布号 |
US2003221069(A1) |
申请公布日期 |
2003.11.27 |
申请号 |
US20020153966 |
申请日期 |
2002.05.22 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
AZEVEDO MICHAEL JOSEPH;SPANEL CAROL;WALLS ANDREW DALE |
分类号 |
G06F12/08;G06F12/12;(IPC1-7):G06F12/12 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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