| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a signal processing apparatus with a small circuit scale, a non-integral frequency divider and a fractional N PLL (phase lock loop) synthesizer having the same. <P>SOLUTION: An adder 8 and a delay device 10 constitute a 9-bit accumulator, output of an adder 2 is inputted and output of 3-input NAND gate 30 is connected with the remaining least significant bit input. An adder 13 and a delay device 15 constitute a 6-bit accumulator and output of the adder 8 is inputted. An adder 18 and a delay device 20 constitute a 4-bit accumulator and output of the adder 13 is inputted. Output of the delay device 20 is inputted in the 3-input NAND gate 30. Overflow signals 22 to 25 of each accumulator are inputted in a signal processing section 27, the sum of the overflow signal 22, first-order differentiation of the overflow signal 23, second-order differentiation of the overflow signal 24 and third-oder differentiation of the overflow signal 25 is obtained and the result is outputted from an output terminal 28. <P>COPYRIGHT: (C)2004,JPO |
